With increasing popularity of electronic devices, such as laptop computers, portable digital assistants, digital cameras, mobile phones, digital audio players, video game consoles and the like, demand for nonvolatile memories are on the rise. Nonvolatile memories come in various types, including flash memories. Flash memories are widely used nowadays for fast information storage in electronic devices such as those mentioned above. A flash memory cell is generally programmed by storing charge on a floating gate. The charge may thereafter remain on the gate for an indefinite period even after power has been removed from the flash memory device. Flash memory devices are therefore nonvolatile.
Charge is stored on the floating gate by applying appropriate voltages to the control gate and the drain or source. For example, negative charge can be placed on the floating gate by grounding the source while applying a sufficiently large positive voltage to the control gate to attract electrons, which tunnel through the gate oxide to the floating gate from the channel region.
A flash memory cell can be read by applying a voltage to the control gate that is positive with respect to the source. The amount of charge stored on the flash memory cell determines the magnitude of the voltage that must be applied to the control gate to allow the flash memory cell to conduct current between the source and the drain. As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases thus increasing the magnitude of the voltage that must be applied to the control gate to allow the flash memory cell to conduct current. During a read operation, a read voltage is applied to the control gate that is large enough to render the cell conductive if insufficient charge is stored on the floating gate, but not large enough to render the cell conductive if sufficient charge is stored on the floating gate. During the read operation, the drain, which is used as the output terminal of the cell, is precharged to a positive voltage, and the source is coupled to ground. Therefore, if the floating gate of the flash memory cell is sufficiently charged, the drain will remain at the positive voltage. If the floating gate of the flash memory cell is not sufficiently charged, the cell will ground the drain.
Before a flash memory cell can be programmed, it may be erased by removing charge from the floating gate. The cell can be erased by applying a gate-to-source voltage to the cell that has a polarity opposite that used for programming. For example, the control gate can be grounded, and a large positive voltage applied to the source to cause the electrons to tunnel through the gate oxide and deplete charge from the floating gate. In another approach, a relatively large negative voltage is applied to the control gate, and a positive voltage, such as a supply voltage, is applied to the source region.
A typical flash memory device includes a memory array containing a large number of flash memory cells arranged in rows and columns. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic flash memory cell configuration of each is arranged. A typical flash memory array may include a large number of flash memory cells divided into a number of blocks. Each block may include a number of rows, with the cells in the same row having their control gates coupled to a common word line. Cells in the same column may have their sources and drains connected to each other in series. Thus all of the memory cells in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell in the block is coupled to a bit line through a select gate transistor. Each of the bit lines output a respective bit line signal BL1-BLN indicative of the data bit stored in the respective column of the array. The bit lines may extend through multiple blocks to respective sense amplifiers.
The storage capacity of a flash memory array can be increased by storing multiple bits of data in each flash memory cell. This can be accomplished by storing multiple levels of charge on the floating gate of each cell. These memory devices are commonly referred to as multi-bit or multi-level flash memory cells, known as “MLC memory cells.” In MLC cells, multiple bits of binary data corresponding to distinct threshold voltage levels defined over respective voltage ranges are stored within a single cell. Each distinct threshold voltage level corresponds to a respective combination of data bits. Specifically, the number N of bits requires 2N distinct threshold voltage levels. For example, for a flash memory cell to store 2 bits of data, 4 distinct threshold voltage levels corresponding to bit states 00, 01, 10, and 11 are needed. When reading the state of the memory cell, the threshold voltage level for which the memory cell conducts current corresponds to a combination of bits representing data programmed into the cell. The two or more bits stored in each flash memory cell may be adjacent bits in the same page of data. However, more frequently, one bit is treated as a bit in one page of data, and the other bit is treated as the corresponding bit in an adjacent page of data. The bit states assigned to respective charge levels are normally the same for all rows of memory cells in an array. The bit states assigned to the flash memory cells in the array are usually implemented in hardware and thus cannot be changed during operation of the flash memory device.
Memory devices may utilize a relatively high voltage for read and program operations. In one example, 5V may be used for a read operation and 20V for a program operation. These voltages may be generated internally on the memory device from an externally-supplied voltage. The externally-supplied voltage may be 3V in one example. The line drivers and sense amplifiers used for read and program operations may operate using a boosted voltage generated based on this externally-supplied voltage.
Input and output buffer circuits on memory devices generally may need to drive an input/output bus coupled to the memory device. Because the bus may have a significant capacitance associated with it, the voltage used to drive the bus should generally be low. In some examples, the externally-supplied voltage used to generate the boosted voltage for read and program operations may be too high to be desirable for use by the input/output buffers.
Accordingly, memory devices may have a dual power supply. One externally-supplied voltage, generally referred to as Vcc_io may be used to operate power input/output circuitry and drive an input/output bus. In one example Vcc_io may be 1.8V. A second externally-supplied voltage, generally referred to as Vcc_peri may be used to power peripheral circuitry, such as line drivers and amplifiers used in read and program operations for the memory device.
FIG. 1 is a schematic illustration of a dual power supply memory device in accordance with the prior art. The memory device 100 may include a memory array 110 that may include any number of memory cells. Peripheral circuits 115 may be coupled to the memory array 110 and configured to read and program data into and out of the memory array 110. The peripheral circuits 115 are configured to receive an externally-supplied voltage Vcc_peri. As mentioned above, the peripheral circuits 115 may include one or more voltage boost circuits that may boost the voltage of Vcc_peri to a voltage used for reading or programming the memory array 110. I/O circuits 120 may be coupled to the peripheral circuits 115 and an I/O bus 125. The I/O circuits 125 may include buffer circuits which receive data from the bus 125 or drive data onto the bus 125. The I/O circuits are configured to receive a second externally supplied voltage Vcc_io. The Vcc_io voltage may be different than the Vcc_peri voltage. In particular, as mentioned above, the Vcc_io voltage may be lower than the Vcc_peri voltage. The I/O bus 125 is coupled to a memory controller 130.